Semiconductor integrated circuits can include a variety of components, including transistors. Such circuits can also include metal lines and contacts that connect the components in the desired manner in order to form a functional, interconnected, and integrated circuit. Fabrication of such circuitry is often done layer upon layer on a semiconductor substrate, e.g., starting with a semiconductor wafer.
For example, a transistor can be formed on and in a semiconductor substrate to include a gate structure on the substrate and doped source and drain structures in the substrate. The structures are then covered and surrounded by an interlayer dielectric layer. Holes are formed through the interlayer dielectric layer extending down to the gate structure as well as the doped source and drain structures. These holes are then filled with a conductive material to form interconnects (also referred to as contacts or vias) for connection to one or more other circuit components, as needed.
Forming the holes to be filled with conductive material does not create a straight cylindrical shaped hole. Rather, the hole becomes narrower the deeper it extends. Because the gates and doped regions are at different heights, the holes for the doped region and the holes for the gates may have different sizes. Specifically, because the holes extending to the doped region are deeper, they may be wider on the top than the holes that extend to the gate electrodes.
The difference in hole size has an effect on pattern design. Particularly, the critical dimension, which relates to the amount of space allowed between holes, can be different for the holes that extend to the doped regions from the holes that extend to the gates. It is desirable to reduce this difference to allow for better overlay budget and critical dimension control.